1. Technical Field
The present invention relates, in general, to junction barrier Schottky rectifiers or diodes with a vertical p+-n junction and, in particular, to such devices having an epitaxially grown drift layer and epitaxially overgrown drift regions forming a p+-n junction which may or may not be buried and self-planarized Schottky contact regions. The devices can be formed in a wide band-gap semiconductor material such as silicon carbide.
2. Background of the Technology
Silicon Carbide (SiC), a wide band-gap semiconductor material, is very attractive for use in high-power, high-temperature, and/or radiation resistant electronics. SiC power switches are logical candidates for these applications due to their excellent material physical properties such as wide energy band-gap, high breakdown field strength, high saturated electron drift velocity and high thermal conductivity compared to the conventional silicon counter part. In addition to the above advantages, SiC power devices can operate with lower specific on-resistance than conventional silicon power devices [1]. SiC unipolar devices are expected to replace Si bipolar switches and rectifiers in the 600-3000 V range in the very near feature.
Generally speaking, there are three types of rectifiers [2]: (1) Schottky diodes, which offer a low effective turn-on voltage hence low on-state losses and extremely high switching speed due to primarily majority carrier conduction resulting in no diffusion capacitance [3] and thereby no real reverse recovery on turning off as well as no forward voltage overshoot on turning on, but suffer from high leakage current; (2) P-i-N diodes, which offer low leakage current but show reverse recovery charge during switching; and (3) Junction Barrier Schottky (JBS) diodes which offers Schottky-like on-state and switching characteristics, and PiN-like off-state characteristics by screening the Schottky surface from the high electric field [4]. In conventional high voltage (>600 V) circuits using Si PiN diodes, the primary source of power loss is the dissipation of reverse recovery charge during the turn-off of the rectifier. A fast recovery from SiC JBS diodes allows the design of packages with much lower thermal requirements for both the rectifier and the switch, and is expected to increase in the power density of circuits by >3×.
Because of the fundamental differences in material properties and processing technologies, traditional Si or GaAs microelectronics technologies in power rectifiers (or diodes) can not be easily transferred to SiC. A number of reports of SiC rectifiers have appeared in the last several decades (e.g., [2-6]).
U.S. Pat. No. 4,982,260 describes defining p-type emitter regions by etching through a heavily doped p-type well created by diffusion. However, since diffusion of dopants into SiC occurs very slowly at even extremely high temperatures, as a practical matter, a p-type well can only be formed in n-type SiC by ion implantation which can result in low minority carrier lifetime due to damage caused by implantation.
An example of a SiC Junction Barrier Schottky (JBS)/Merged P-I-N Schottky (MPS) grid can be found in U.S. Pat. No. 6,524,900 B2. This device has Schottky metal deposited on implanted p-type islands defined by plasma etching through an epitaxially grown layer. However, this structure is unable to effectively protect itself from a surge current in case of absence of p-type ohmic contacts on p-type regions and insufficient conductivity modulation caused by low doping of p-type regions.
An example of a junction barrier rectifier employing an implanted P+ region to form p-n junction can be found in U.S. Pat. No. 6,104,043. In this case, although Ohmic contacts are formed on heavily doped implanted p-type regions, the conductivity modulation in the drift region of such a structure suffers from low minority carrier lifetime caused by residual implantation damages even after high-temperature thermal anneal.
To date, most of the obstacles to low-cost volume manufacturing can be traced back to the p+-n junction level process steps. Also, the heavily doped p-type region for Ohmic contact can be difficult to fabricate in SiC because of the large band-gap of SiC. To obtain an abrupt p+-n junction for both conductivity modulation and Ohmic contact in SiC junction barrier Schottky diodes, ion implantation is often used to form the P+ region. Damage induced during ion implantation and post implantation anneal at very high temperatures (e.g., temperatures>=1500° C.) can cause the reverse leakage current of p-n junction to increase and tend to degrade the surface of SiC on which the Schottky contact is to be made. Damage resulting from these processing steps can greatly affect device performance including forward conduction and blocking capability. It is also difficult to have a precise control of p+-n junction depth by ion implantation because of a combination of uncertainties on actual depth profile of implantation tail, defect density, redistribution of implanted ions after annealing, and ionization percentage of dopant atoms and point defects under different bias and/or temperature stress.
To eliminate these drawbacks, alternative methods of forming a p+-n junction can be used. One method is to selectively grow P+ gate regions epitaxially as disclosed in U.S. Pat. No. 6,767,783. Another method of forming a p+-n junction is to epitaxially regrow a P+ layer on top of an trench-etched N− drift layer, followed by a plasma etch-back or chemical-mechanical polishing or other planarization method to expose the N− drift region for Schottky metal contact. A similar method is disclosed in U.S. Pat. No. 6,897,133 B2. In the device described in this reference, however, lightly doped P regions are used to form the p-n junction. Also in this device, the epitaxially grown p-type regions do not form JFET regions that may significantly limit current conduction under both normal and surge current operating conditions.
Accordingly, there still exists a need for improved methods of manufacturing semiconductor devices.